Content
AT90S2313 worksheet

	Registers Instructions Reset and Interrupt handling Equipment: EEPROM UART Analog Comparator I/O ports

About this help file...

This help file was made for the daily work with the Atmel AVR microcontroller AT90S2313 and contains all what You really need for the daily work. The main reason for this help file was, that PDF files are are good for printouts but terrific for non-printed use (dirty display, big file size, slow opening and a lot of other reasons).

The text was taken from the original datasheet PDF file. Some text is added, some removed, changed or sorted in another way just as I found it usefull. For the very basics You should read the original datasheet PDF file.

The help file was made by Roland Walter. Hints, tips and bug reports send to support@rowalt.de

New versions You will find at www.rowalt.de/mc/

The help file is freeware.


Reset and Interrupt handling
Overview: Reset and Interrupt handling

The AT90S2313 provides 10 different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space.

All the interrupts are assigned individual enable bits that must be set (one) together with the I-bit in the Status Register in order to enable the interrupt.

The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The complete list of vectors is shown in the following table. The list also determines the priority levels of the different interrupts. The lower the address, the higher the priority level. RESET has the highest priority, and next is INT0 (the External Interrupt Request 0), etc.

Reset and Interrupt Vectors:

Vector No.	Program Address	Source	Interrupt Definition
1	$000	RESET	Hardware Pin, Power-on Reset and Watchdog Reset
2	$001	INT0	External Interrupt Request 0
3	$002	INT1	External Interrupt Request 1
4	$003	TIMER1 CAPT1	Timer/Counter1 Capture Event
5	$004	TIMER1 COMP1	Timer/Counter1 Compare Match
6	$005	TIMER1 OVF1	Timer/Counter1 Overflow
7	$006	TIMER0 OVF0	Timer/Counter0 Overflow
8	$007	UART, RX	UART, RX Complete
9	$008	UART, UDRE	UART Data Register Empty
10	$009	UART, TX	UART, TX Complete
11	$00A	ANA_COMP	Analog Comparator

The most typical and general program setup for the Reset and Interrupt vector addresses are:

Address Labels Code                Comments

$000           rjmp RESET          ;Reset Handler

$001           rjmp EXT_INT0       ;IRQ0 Handler

$002           rjmp EXT_INT1       ;IRQ1 Handler

$003           rjmp TIM_CAPT1      ;Timer1 Capture Handler

$004           rjmp TIM_COMP1      ;Timer1 Compare Handler

$005           rjmp TIM_OVF1       ;Timer1 Overflow Handler

$006           rjmp TIM_OVF0       ;Timer0 Overflow Handler

$007           rjmp UART_RXC       ;UART RX Complete Handler

$008           rjmp UART_DRE       ;UDR Empty Handler

$009           rjmp UART_TXC       ;UART TX Complete Handler

$00a           rjmp ANA_COMP       ;Analog Comparator Handler

;

$00b    MAIN:  ldi r16,low(RAMEND) ;Main program start

$00c           out SPL,r16

$00d           <instr> xxx

...  ...       ...

Reset Sources

The AT90S2313 has three sources of reset:

•	Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (VPOT).

•	External Reset. The MCU is reset when a low level is present on the RESET pin for more than 50 ns.

•	Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.

During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000. The instruction placed in address $000 must be an RJMP (relative jump) instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. The following table defines the timing and electrical parameters of the reset circuitry.

Reset Characteristics (VCC = 5.0V):

Symbol	Parameter	Min	Typ	Max	Units
VPOT(1)	Power-on Reset Threshold Voltage (rising)	1.0	1.4	1.8	V
	Power-on Reset Threshold Voltage (falling)	0.4	0.6	0.8	V
VRST	RESET Pin Threshold Voltage		-	0.85 VCC	V
tTOUT	Reset Delay Time-out Period FSTRT Unprogrammed	11.0	16.0	21.0	ms
tTOUT	Reset Delay Time-out Period FSTRT Programmed	0.25	0.28	0.31	ms
Note: 1. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling).

The user can select the start-up time according to typical oscillator start-up. The number of WDT oscillator cycles used for each time-out is shown in the following table. The frequency of the Watchdog Oscillator is voltage-dependent (see Typical Characteristics” in datasheet).

Number of Watchdog Oscillator Cycles:

FSTRT	Time-out at VCC = 5V	Number of WDT Cycles
Programmed	0.28 ms	256
Unprogrammed	16.0 ms	16K

Power-on Reset

A Power-on Reset (POR) circuit ensures that the device is reset from power-on. An internal timer is clocked from the Watchdog Timer. This timer prevents the MCU from starting until after a certain period after VCC has reached the Power-on Threshold voltage (VPOT). The FSTRT Fuse bit in the Flash can be programmed to give a shorter start-up time if a ceramic resonator or any other fast-start oscillator is used to clock the MCU.

If the built-in start-up delay is sufficient, RESET can be connected to VCC directly or via an external pull-up resistor. By holding the RESET pin low for a period after VCC has been applied, the Power-on Reset period can be extended.

External Reset

An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage (VRST) on its positive edge, the delay timer starts the MCU after the Time-out period tTOUT has expired.

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one XTAL cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. For details on operation see Watchdog Timer Control Register WDTCR.

Interrupt Handling

The AT90S2313 has two 8-bit Interrupt Mask control registers: the GIMSK (General Interrupt Mask register) and the TIMSK (Timer/Counter Interrupt Mask register).

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable interrupts. The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.

For interrupts triggered by events that can remain static (e.g., the Output Compare Register1 matching the value of Timer/Counter1), the interrupt flag is set when the event occurs. If the interrupt flag is cleared and the interrupt condition persists, the flag will not be set until the event occurs the next time.

When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a logical 1” to the flag bit position(s) to be cleared.

If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software.

If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority.

Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is active.

Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles, minimum. Four clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this 4-clock-cycle period, the Program Counter (2 bytes) is pushed onto the stack, and the Stack Pointer is decremented by 2. The vector is normally a relative jump to the interrupt routine, and this jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (2 bytes) is popped back from the stack, the Stack Pointer is incremented by 2, and the I-flag in SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.


EEPROM overview
Overview: EEPROM

EEPROM Read/Write Access

The EEPROM access registers are accessible in the I/O space.

The write access time is in the range of 2.5 - 4 ms, depending on the VCC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains code that writes the EEPROM, some precaution must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on powerup/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. CPU operation under these conditions may cause the Program Counter to perform unintentional jumps and eventually execute the EEPROM write code. To secure EEPROM integrity, the user is advised to use an external under-voltage reset circuit in this case.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed.

Prevent EEPROM Corruption

During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board-level systems using the EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly if the supply voltage for executing instructions is too low.

EEPROM data corruption can easily be avoided by following these design recommendations (one is sufficient):

1.	Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This is best done by an external low VCC Reset Protection circuit, often referred to as a Brown-out Detector (BOD). Please refer to the AVR 180 application note for design considerations regarding power-on reset and low-voltage detection.

2.	Keep the AVR core in Power-down Sleep Mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting the EEPROM registers from unintentional writes.

3.	Store constants in Flash memory if the ability to change memory contents from software is not required. Flash memory cannot be updated by the CPU and will not be subject to corruption.

Registers:

EECR	EEPROM Control Register

EEDR	EEPROM Data Register

EEAR	EEPROM Address Register


UART overview
Overview: UART

The AT90S2313 features a full duplex (separate receive and transmit registers) Universal Asynchronous Receiver and Transmitter (UART). The main features are:

•	Baud Rate Generator that can generate a large number of baud rates (bps)

•	High baud rates at low XTAL frequencies

•	8 or 9 bits data

•	Noise filtering

•	Overrun detection

•	Framing error detection

•	False start bit detection

•	Three separate interrupts on TX complete, TX data register empty and RX complete

Data transmission

Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register (UDR). Data is transferred from UDR to the Transmit shift register when:

•	A new character has been written to UDR after the stop bit from the previous character has been shifted out. The shift register is loaded immediately.

•	A new character has been written to UDR before the stop bit from the previous character has been shifted out. The shift register is loaded when the stop bit of the character currently being transmitted has been shifted out.

If the 10(11)-bit Transmitter shift register is empty, data is transferred from UDR to the shift register. At this time the UDRE (UART Data Register Empty) bit in the UART Status Register (USR) is set. When this bit is set (one), the UART is ready to receive the next character. At the same time as the data is transferred from UDR to the 10(11)-bit shift register, bit 0 of the shift register is cleared (start bit) and bit 9 or 10 is set (stop bit). If 9-bit data word is selected (the CHR9 bit in the UART Control Register [UCR] is set), the TXB8 bit in UCR is transferred to bit 9 in the Transmit shift register.

On the Baud Rate clock following the transfer operation to the shift register, the start bit is shifted out on the TXD pin. Then follows the data, LSB first. When the stop bit has been shifted out, the shift register is loaded if any new data has been written to the UDR during the transmission. During loading, UDRE is set. If there is no new data in the UDR register to send when the stop bit is shifted out, the UDRE flag will remain set until UDR is written again. When no new data has been written, and the stop bit has been present on TXD for one bit length, the TX Complete Flag (TXC) in USR is set.

The TXEN bit in UCR enables the UART transmitter when set (one). When this bit is cleared (zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART Transmitter will be connected to PD1, which is forced to be an output pin regardless of the setting of the DDD1 bit in DDRD.

Data Reception

The receiver front-end logic samples the signal on the RXD pin at a frequency of 16 times the baud rate. While the line is idle, one single sample of logical 0” will be interpreted as the falling edge of a start bit, and the start bit detection sequence is initiated.

Let sample 1 denote the first zero-sample. Following the 1-to-0 transition, the receiver samples the RXD pin at samples 8, 9 and 10. If two or more of these three samples are found to be logical 1”s, the start bit is rejected as a noise spike and the receiver starts looking for the next 1-to-0 transition.

If, however, a valid start bit is detected, sampling of the data bits following the start bit is performed. These bits are also sampled at samples 8, 9 and 10. The logical value found in at least two of the three samples is taken as the bit value. All bits are shifted into the transmitter shift register as they are sampled.

When the stop bit enters the receiver, the majority of the three samples must be 1” to accept the stop bit. If two or more samples are logical 0”s, the Framing Error (FE) flag in the UART Status Register (USR) is set. Before reading the UDR register, the user should always check the FE bit to detect Framing Errors.

Whether or not a valid stop bit is detected at the end of a character-reception cycle, the data is transferred to UDR and the RXC flag in USR is set. UDR is in fact two physically separate registers; one for transmitted data and one for received data. When UDR is read, the Receive Data register is accessed, and when UDR is written, the Transmit Data register is accessed. If 9-bit data word is selected (the CHR9 bit in the UART Control Register [UCR] is set), the RXB8 bit in UCR is loaded with bit 9 in the Transmit shift register when data is transferred to UDR.

If, after having received a character, the UDR register has not been read since the last receive, the OverRun (OR) flag in UCR is set. This means that the last data byte shifted into the shift register could not be transferred to UDR and has been lost. The OR bit is buffered and is updated when the valid data byte in UDR is read. Thus, the user should always check the OR bit after reading the UDR register in order to detect any overruns if the baud rate is high or CPU load is high.

When the RXEN bit in the UCR register is cleared (zero), the receiver is disabled. This means that the PD0 pin can be used as a general I/O pin. When RXEN is set, the UART Receiver will be connected to PD0, which is forced to be an input pin regardless of the setting of the DDD0 bit in DDRD. When PD0 is forced to input by the UART, the PORTD0 bit can still be used to control the pull-up resistor on the pin.

When the CHR9 bit in the UCR register is set, transmitted and received characters are nine bits long plus start and stop bits. The ninth data bit to be transmitted is the TXB8 bit in UCR register. This bit must be set to the wanted value before a transmission is initiated by writing to the UDR register. The ninth data bit received is the RXB8 bit in the UCR register.

Registers:

UBRR	UART Baud Rate Register

UCR	UART Control Register

USR	UART Status Register

UDR	UART I/O Data Register


Analog Comparator
Overview: Analog Comparator

The Analog Comparator compares the input values on the positive input AIN0 (PB0) and the negative input PB1(AIN1). When the voltage on the positive input PB0 (AIN0) is higher than the voltage on the negative input PB1 (AIN1), the Analog Comparator Output, ACO is set (one). The comparators output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt exclusive to the Analog Comparator. The user can select interrupt triggering on comparator output rise, fall or toggle.

Registers:

ACSR 	Analog Comparator Control and Status Register


I/O ports
Overview: I/O Ports

All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies for changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).

The AT90S2313 has two ports: Port B and Port D. Both ports are bi-directional I/O ports.

Three I/O memory address locations are allocated for the ports:

		Port B	Port D
	Data Register (read/write)	PORTB	PORTD
	Data Direction Register (read/write)	DDRB	DDRD
	Input Pins (read only)	PINB	PIND

All port pins have individually selectable pull-up resistors. The port output buffers can sink 20 mA and thus drive LED displays directly. When the pins are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.

The Input Pins addresses (PINB/PIND) are no registers; these addresses enables access to the physical value on each port pin. When reading PORTB/PORTD, the port Data Latch is read, and when reading PINB/PIND, the logical values present on the pins are read.

Port as General Digital I/O

All port pins have equal functionality when used as digital I/O pins.

The bits in the Data Direction Register selects the direction of this pin. If the bit is set (one), the pin is configured as an output pin. If the bit is cleared (zero), the pin is configured as an input pin.

If a Data Register bit is set (one) when the pin is configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up resistor off, the Data Register has to be cleared (zero) or the pin has to be configured as an output pin.

The port pins are tri-stated when a reset condition becomes active, even if the clock is not active.

Effects on port pins:

DDBn DDDn	PORTBn PORTDn	I/O	Pull-up	Comment
0	0	Input	No	Tri-state (High-Z)
0	1	Input	Yes	PBn/PDn will source current if external pulled low
1	0	Output	No	Push-pull Zero Output
1	1	Output	No	Push-pull One Output
Note: n: 7,6…0, pin number.

Port alternate functions

The port pins with alternate functions are shown below. When the pins are used for the alternate function, the Data Direction Registers and Data Registers have to be set according to the alternate function description.

The alternate pin functions of Port B are:

PB7	SCK, Clock input pin for memory up/downloading.

PB6	MISO, Data output pin for memory uploading.

PB5	MOSI, Data input pin for memory downloading.

PB3	OC1, Output Compare Match Output. The PB3 pin can serve as an external output for timer 1 compare match. The PB3 pin has to be configured as an output (DDB3 is set [one]) to serve this function. See the timer description for further details, and how to enable the output.

PB1	AIN1, Analog Comparator Negative Input. When configured as an input (DDB1 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB1 is cleared [zero]), this pin also serves as the negative input of the on-chip Analog Comparator.

PB0	AIN0, Analog Comparator Positive Input. When configured as an input (DDB0 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB0 is cleared [zero]), this pin also serves as the positive input of the on-chip Analog Comparator.

The alternate functions of Port D are:

PD6	Timer/Counter1 Input Capture pin. See the Timer/Counter1 description for further details.

PD5	T1, Timer 1 clock source. See the Timer description for further details.

PD4	T0, Timer/Counter0 clock source. See the Timer description for further details.

PD3	INT1, External Interrupt Source 1. The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.

PD2	INT0, External Interrupt Source 0. The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.

PD1	Transmit Data (Data output pin for the UART). When the UART transmitter is enabled, this pin is configured as an output regardless of the value of DDRD1.

PD0	Receive Data (Data input pin for the UART). When the UART receiver is enabled, this pin is configured as an input regardless of the value of DDRD0. When the UART forces this pin to be an input, a logical 1” in PORTD0 will turn on the internal pull-up.


Register/Memory overview

Register name	SRAM address	I/O address	Comment
R00-R15	$00-$0F	-	General purpose working register. Not for instructions which make arithmetical or logical operations with immediates (SBCI, SUBI, CPI, ANDI, ORI) or load immediates (LDI).
R16-R25	$10-$19	-	General purpose working registers
R26 / XL	$1A	-	General purpose working register. Extended function: X register, LowByte
R27 / XH	$1B	-	General purpose working register. Extended function: X register, HighByte
R28 / YL	$1C	-	General purpose working register. Extended function: Y register, LowByte
R29 / YH	$1D	-	General purpose working register. Extended function: Y register, HighByte
R30 / ZL	$1E	-	General purpose working register. Extended function: Z register, LowByte
R31 / ZH	$1F	-	General purpose working register. Extended function: Z register, HighByte
-	$20-$27	$00-$07	Not used in AT90S2313
ACSR	$28	$08	Analog Comparator Control and Status Register
UBRR	$29	$09	UART Baud Rate Register
UCR	$2A	$0A	UART Control Register
USR	$2B	$0B	UART Status Register
UDR	$2C	$0C	UART I/O Data Register
-	$2D-$2F	$0D-$09	Not used in AT90S2313
PIND	$30	$10	Input Pins, Port D
DDRD	$31	$11	Data Direction Register, Port D
PORTD	$32	$12	Data Register, Port D
	$33-$35	$13-$15	Not used in AT90S2313
PINB	$36	$16	Input Pins, Port B
DDRB	$37	$17	Data Direction Register, Port B
PORTB	$38	$18	Data Register, Port B
-	$39-$3B	$19-$1B	Not used in AT90S2313
EECR	$3C	$1C	EEPROM Control Register
EEDR	$3D	$1D	EEPROM Data Register
EEAR	$3E	$1E	EEPROM Address Register
-	$3F-$40	$1F-$20	Not used in AT90S2313
WDTCR	$41	$21	Watchdog Timer Control Register
-	$42-$43	$22-$23	Not used in AT90S2313
ICR1L	$44	$24	Timer/Counter 1 Input Capture Register Low Byte
ICR1H	$45	$25	Timer/Counter 1 Input Capture Register High Byte
-	$46-$49	$25-$29	Not used in AT90S2313
OCR1AL	$4A	$2A	Output Compare Register 1 Low Byte
OCR1AH	$4B	$2B	Output Compare Register 1 High Byte
TCNT1L	$4C	$2C	Timer/Counter 1 Low Byte
TCNT1H	$4D	$2D	Timer/Counter 1 High Byte
TCCR1B	$4E	$2E	Timer/Counter 1 Control Register B
TCCR1A	$4F	$2F	Timer/Counter 1 Control Register A
-	$50-$51	$30-$31	Not used in AT90S2313
TCNT0	$52	$32	Timer/Counter 0 (8-bit)
TCCR0	$53	$33	Timer/Counter 0 Control Register
-	$54	$34	Not used in AT90S2313
MCUCR	$55	$35	MCU general Control Register
-	$56-$57	$36-$37	Not used in AT90S2313
TIFR	$58	$38	Timer/Counter Interrupt Flag register
TIMSK	$59	$39	Timer/Counter Interrupt MaSK register
GIFR	$5A	$3A	General Interrupt Flag Register
GIMSK	$5B	$3B	General Interrupt MaSK register
-	$5C	$3C	Not used in AT90S2313
SPL	$5D	$3D	Stack Pointer Low
-	$5E	$3E	Not used in AT90S2313
SREG	$5F	$3F	Status Register
-	$60-$DF	-	Internal SRAM data memory (128 bytes)

The I/O address is for use with I/O instructions only. These are the instructions IN and OUT which You can use for all registers in I/O address space $00-$3F and the instructions SBI, CBI, SBIS, SBIC which You can use with registers in I/O address space $00-$1F only. For I/O register access with other instructions You must use the SRAM addresses (Hint: SRAM = I/O + $20).


SREG
SREG - Status Register (I/O address: $3F, SRAM address: $5F)

Bit	R/W	Name	Init	Comment
7	R/W	I	0	Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the global interrupt enable bit is cleared (zero), none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.
6	R/W	T	0	Bit Copy Storage The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.
5	R/W	H	0	Half-carry Flag The half-carry flag H indicates a half-carry in some arithmetic operations. See the Instruction Set description for detailed information.
4	R/W	S	0	Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the negative flag N and the twos complement overflow flag V. See the Instruction Set description for detailed information.
3	R/W	V	0	Twos Complement Overflow Flag The twos complement overflow flag V supports twos complement arithmetics. See the Instruction Set description for detailed information.
2	R/W	N	0	Negative Flag The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set description for detailed information.
1	R/W	Z	0	Zero Flag The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set description for detailed information.
0	R/W	C	0	Carry Flag The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set description for detailed information. Note that the Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software.


SPL
SPL - Stack Pointer Low (I/O address: $3D, SRAM address: $5D)

Bit	R/W	Name	Init	Comment
7	R/W	SP7	0
6	R/W	SP6	0
5	R/W	SP5	0
4	R/W	SP4	0
3	R/W	SP3	0
2	R/W	SP2	0
1	R/W	SP1	0
0	R/W	SP0	0

SPL is the stack pointer of the AT90S2313. 8 bits are used to address the 128 bytes of SRAM in the I/O space locations $60 - $DF.

The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt stacks are located. This stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above $60. The Stack Pointer is decremented by 1 when data is pushed onto the stack with the PUSH instruction, and it is decremented by 2 when an address is pushed onto the stack with subroutine calls and interrupts. The Stack Pointer is incremented by 1 when data is popped from the stack with the POP instruction, and it is incremented by 2 when an address is popped from the stack with return from subroutine RET or return from interrupt RETI.


GIMSK
GIMSK - General Interrupt Mask Register (I/O address: $3B, SRAM address: $5B)

Bit	R/W	Name	Init	Comment
7	R/W	INT1	0	External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also External Interrupts”.
6	R/W	INT0	0	External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also External Interrupts.”
5	R	-	0	Reserved. Always read as zero.
4	R	-	0	Reserved. Always read as zero.
3	R	-	0	Reserved. Always read as zero.
2	R	-	0	Reserved. Always read as zero.
1	R	-	0	Reserved. Always read as zero.
0	R	-	0	Reserved. Always read as zero.


GIFR
GIFR - General Interrupt FLAG Register (I/O address: $3A, SRAM address: $5A)

Bit	R/W	Name	Init	Comment
7	R/W	INTF1	0	External Interrupt Flag1 When an edge on the INT1 pin triggers an interrupt request, the corresponding interrupt flag, INTF1, becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT1 bit in GIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical 1” to it. The flag is always cleared when INT1 is configured as level interrupt.
6	R/W	INTF0	0	External Interrupt Flag0 When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt flag, INTF0, becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT0 bit in GIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical 1” to it. The flag is always cleared when INT0 is configured as level interrupt.
5	R/W	-	0	Reserved. Always read as zero.
4	R/W	-	0	Reserved. Always read as zero.
3	R/W	-	0	Reserved. Always read as zero.
2	R/W	-	0	Reserved. Always read as zero.
1	R/W	-	0	Reserved. Always read as zero.
0	R/W	-	0	Reserved. Always read as zero.

Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is active.


TIMSK
TIMSK - Timer/Counter Interrupt Mask Register (I/O address: $39, SRAM address: $59)

Bit	R/W	Name	Init	Comment
7	R/W	TOIE1	0	Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding interrupt (at vector $005) is executed if an overflow in Timer/Counter1 occurs (i.e., when the TOV1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
6	R/W	OCIE1A	0	Timer/Counter1 Output Compare Match Interrupt Enable When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Compare Match Interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a compare match in Timer/Counter1 occurs (i.e., when the OCF1A bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
5	R	-	0	Reserved. Always read as zero.
4	R	-	0	Reserved. Always read as zero.
3	R/W	TICIE1	0	Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on PD6(ICP) (i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
2	R	-	0	Reserved. Always read as zero.
1	R/W	TOIE0	0	Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter0 occurs (i.e., when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register [TIFR]).
0	R	-	0	Reserved. Always read as zero.


TIFR
TIFR - Timer/Counter Interrupt Flag Register (I/O address: $38, SRAM address: $58)

Bit	R/W	Name	Init	Comment
7	R/W	TOV1	0	Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logical 1” to the flag. When the I-bit in SREG and TOIE1 (Timer/Counter1 Overflow Interrupt Enable) and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.
6	R/W	OCF1A	0	Output Compare Flag 1A The OCF1A bit is set (one) when a compare match occurs between the Timer/Counter1 and the data in OCR1A (Output Compare Register1 A). OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logical 1” to the flag. When the I-bit in SREG and OCIE1A (Timer/Counter1 Compare Match Interrupt Enable) and the OCF1A are set (one), the Timer/Counter1 Compare Match Interrupt is executed.
5	R	-	0	Reserved. Always read as zero.
4	R	-	0	Reserved. Always read as zero.
3	R/W	ICF1	0	Input Capture Flag 1 The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the Input Capture Register (ICR1). ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logical 1” to the flag. When the SREG I-bit and TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) and ICF1 are set (one), the Timer/Counter1 Capture Interrupt is executed.
2	R	-	0	Reserved. Always read as zero.
1	R/W	TOV0	0	Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logical 1” to the flag. When the SREG I-bit and TOIE0 (Timer/Counter0 Overflow Interrupt Enable) and TOV0 are set (one), the Timer/Counter0 Overflow Interrupt is executed.
0	R	-	0	Reserved. Always read as zero.


MCUCR
MCUCR - MCU Control Register (I/O address: $35, SRAM address: $55)

Bit	R/W	Name	Init	Comment
7	R	-	0	Reserved. Always read as zero.
6	R	-	0	Reserved. Always read as zero.
5	R/W	SE	0	Sleep Enable The SE bit must be set (one) to make the MCU enter the Sleep Mode when the SLEEP instruction is executed. To avoid the MCU entering the Sleep Mode unless it is the programmers purpose, it is recommended to set the Sleep Enable (SE) bit just before the execution of the SLEEP instruction.
4	R/W	SM	0	Sleep Mode This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode. When SM is set (one), Power-down Mode is selected as Sleep Mode. For details, refer to the paragraph Sleep Modes”.
3 2	R/W R/W	ISC11 ISC10	0 0	ISC11 and ISC10: Interrupt 1 Sense Control Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the GIMSK register is set. The level and edges on the external INT1 pin that activate the interrupt are defined in the following table: ISC11 ISC10 Description 0 0 The low level of INT1 generates an interrupt request. 0 1 Reserved 1 0 The falling edge of INT1 generates an interrupt request. 1 1 The rising edge of INT1 generates an interrupt request. The value on the INT1 pin is sampled before detecting edges. If edge interrupt is selected, pulses with a duration longer than one CPU clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate an interrupt request as long as the pin is held low.
1 0	R/W R/W	ISC01 ISC00	0 0	ISC01 and ISC00: Interrupt 0 Sense Control Bit 1 and Bit 0 Same as ISC11 and ISC10 but for Interrupt 0.

Sleep Modes

To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file, SRAM and I/O memory are unaltered. If a reset occurs during Sleep Mode, the MCU wakes up and executes from the Reset vector.

Idle Mode

When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle Mode, stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external triggered interrupts as well as internal ones like Timer Overflow interrupt and Watchdog reset. If wake-up from the Analog Comparator Interrupt is not required, the Analog Comparator can be powered down by setting the ACD-bit in the Analog Comparator Control and Status Register (ACSR). This will reduce power consumption in Idle Mode. When the MCU wakes up from Idle Mode, the CPU starts program execution immediately.

Power-down Mode

When the SM bit is set (one), the SLEEP instruction forces the MCU into the Powerdown Mode. In this mode, the external oscillator is stopped while the external interrupts and the Watchdog (if enabled) continue operating. Only an external reset, a Watchdog reset (if enabled), an external level interrupt on INT0 or INT1 can wake up the MCU.

Note that when a level-triggered interrupt is used for wake-up from power-down, the low level must be held for a time longer than the reset delay Time-out period tTOUT. Otherwise, the device will not wake up.


TCCR0
TCCR0 - Timer/Counter0 Control Register (I/O address: $33, SRAM address: $53)

Bit	R/W	Name	Init	Comment
7	R	-	0	Reserved. Always read as zero.
6	R	-	0	Reserved. Always read as zero.
5	R	-	0	Reserved. Always read as zero.
4	R	-	0	Reserved. Always read as zero.
3	R	-	0	Reserved. Always read as zero.
2 1 0	R/W R/W R/W	CS02 CS01 CS00	0 0 0	Clock Select0, Bit 2,1 and 0 Define the prescaling source of Timer/Counter0: CS02 CS01 CS00 Description 0 0 0 Stop, the Timer/Counter0 is stopped. 0 0 1 CK 0 1 0 CK/8 0 1 1 CK/64 1 0 0 CK/256 1 0 1 CK/1024 1 1 0 External Pin T0, falling edge 1 1 1 External Pin T0, rising edge

The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter0, transitions on PD4/(T0) will clock the counter even if the pin is configured as an output. This feature can give the user software control of the counting.


TCNT0
TCNT0 -  Timer/Counter0 (I/O address: $32, SRAM address: $52)

Bit	R/W	Name	Init	Comment
7	R/W	MSB	0
6	R/W		0
5	R/W		0
4	R/W		0	Bits 0...7: Timer/Counter0 value
3	R/W		0
2	R/W		0
1	R/W		0
0	R/W	LSB	0

The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the timer clock cycle following the write operation.


TCCR1A
TCCR1A -  Timer/Counter1 Control Register A (I/O address: $2F, SRAM address: $4F)

Bit	R/W	Name	Init	Comment
7 6	R/W R/W	COM1A1 COM1A0	0	Bits 7,6 -  COM1A1, COM1A0: Compare Output Mode1, Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare match in Timer/Counter1. Any output pin actions affect pin OC1 (Output Compare pin 1) (PB3). This is an alternative function to the I/O port, and the corresponding direction control bit must be set (one) to control an output pin. COM1A1 COM1A0 Description 0 0 Timer/Counter1 disconnected from output pin OC1 0 1 Toggle the OC1 output line. 1 0 Clear the OC1 output line (to zero). 1 1 Set the OC1 output line (to one). Note: In PWM mode, these bits have a different function. See register ICR1H/ICR1L for a detailed description.
5	R	-	0	Reserved. Always read as zero.
4	R	-	0	Reserved. Always read as zero.
3	R	-	0	Reserved. Always read as zero.
2	R	-	0	Reserved. Always read as zero.
1 0	R/W R/W	PWM11 PWM10	0 0	Bits 1,0 - PWM11, PWM10: Pulse Width Modulator Select Bits PWM11 PWM10 Description 0 0 PWM operation of Timer/Counter1 is disabled 0 1 Timer/Counter1 is an 8-bit PWM 1 0 Timer/Counter1 is a 9-bit PWM 1 1 Timer/Counter1 is a 10-bit PWM


TCCR1B
TCCR1B -  Timer/Counter1 Control Register B (I/O address: $2E, SRAM address: $4E)

Bit	R/W	Name	Init	Comment
7	R/W	ICNC1	0	Input Capture1 Noise Canceler (4 CKs) When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the ICP (input capture pin) as specified. When the ICNC1 bit is set (one), four successive samples are measured on the ICP (input capture pin), and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is the XTAL clock frequency.
6	R/W	ICES1	0	Input Capture1 Edge Select While the ICES1 bit is cleared (zero), the Timer/Counter1 contents are transferred to the Input Capture Register (ICR1) on the falling edge of the input capture pin (ICP). While the ICES1 bit is set (one), the Timer/Counter1 contents are transferred to the Input Capture Register (ICR1) on the rising edge of the input capture pin (ICP).
5	R	-	0	Reserved. Always read as zero.
4	R	-	0	Reserved. Always read as zero.
3	R/W	CTC1	0	Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match. If the CTC1 control bit is cleared, Timer/Counter1 continues counting and is unaffected by a compare match. Since the compare match is detected in the CPU clock cycle following the match, this function will behave differently when a prescaling higher than 1 is used for the timer. When a prescaling of 1 is used, and the compareA register is set to C, the timer will count as follows if CTC1 is set: ... | C-2 | C-1 | C | 0 | 1 |... When the prescaler is set to divide by 8, the timer will count like this: ... | C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-2 | C-1, C-1, C-1, C-1, C-1, C-1, C-1, C-1 | C, 0, 0, 0, 0, 0, 0, 0 |... In PWM mode, this bit has no effect.
2 1 0	R/W R/W R/W	CS12 CS11 CS10	0 0 0	Bits 2,1,0 - CS12, CS11, CS10: Clock Select1, Bits 2, 1 and 0 The Clock Select1 bits 2, 1 and 0 define the prescaling source of Timer/Counter1: CS12 CS11 CS10 Description 0 0 0 Stop, the Timer/Counter1 is stopped. 0 0 1 CK 0 1 0 CK/8 0 1 1 CK/64 1 0 0 CK/256 1 0 1 CK/1024 1 1 0 External Pin T1, falling edge 1 1 1 External Pin T1, rising edge The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used for Timer/Counter1, transitions on PD5/(T1) will clock the counter even if the pin is configured as an output. This feature can give the user software control of the counting.


TCNT1L and TCNT1H
TCNT1L and TCNT1H -  Timer/Counter1

(TCNT1L: I/O address: $2C, SRAM address: $4C - TCNT1H: I/O address: $2D, SRAM address: $4D)

TCNT1L		TCNT1H
Bit	R/W	Name	Init		Bit	R/W	Name	Init
7	R/W	Bit 7	0		7	R/W	Bit 14 (MSB)	0
6	R/W	Bit 6	0		6	R/W	Bit 14	0
5	R/W	Bit 5	0		5	R/W	Bit 13	0
4	R/W	Bit 4	0		4	R/W	Bit 12	0
3	R/W	Bit 3	0		3	R/W	Bit 11	0
2	R/W	Bit 2	0		2	R/W	Bit 10	0
1	R/W	Bit 1	0		1	R/W	Bit 9	0
0	R/W	Bit 0 (LSB)	0		0	R/W	Bit 8	0

This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A and ICR1. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program or interrupts if interrupts are re-enabled.

•	TCNT1 Timer/Counter1 Write:
When the CPU writes to the high byte TCNT1H, the written data is placed in the TEMP register. Next, when the CPU writes the low byte TCNT1L, this byte of data is combined with the byte data in the TEMP register, and all 16 bits are written to the TCNT1 Timer/Counter1 register simultaneously. Consequently, the high byte TCNT1H must be accessed first for a full 16-bit register write operation.

•	TCNT1 Timer/Counter1 Read:
When the CPU reads the low byte TCNT1L, the data of the low byte TCNT1L is sent to the CPU and the data of the high byte TCNT1H is placed in the TEMP register.
When the CPU reads the data in the high byte TCNT1H, the CPU receives the data in the TEMP register. Consequently, the low byte TCNT1L must be accessed first for a full 16-bit register read operation.

The Timer/Counter1 is realized as an up or up/down (in PWM mode) counter with read and write access. If Timer/Counter1 is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value.


OCR1AL and OCR1AH
OCR1AL and OCR1AH -  Timer/Counter1 Output Compare Register A

(TCCR1L: I/O address: $2A, SRAM address: $4A - TCCR1H: I/O address: $2B, SRAM address: $4B)

OCR1AL		OCR1AH
Bit	R/W	Name	Init		Bit	R/W	Name	Init
7	R/W	Bit 7	0		7	R/W	Bit 14 (MSB)	0
6	R/W	Bit 6	0		6	R/W	Bit 14	0
5	R/W	Bit 5	0		5	R/W	Bit 13	0
4	R/W	Bit 4	0		4	R/W	Bit 12	0
3	R/W	Bit 3	0		3	R/W	Bit 11	0
2	R/W	Bit 2	0		2	R/W	Bit 10	0
1	R/W	Bit 1	0		1	R/W	Bit 9	0
0	R/W	Bit 0 (LSB)	0		0	R/W	Bit 8	0

The output compare register is a 16-bit read/write register.

The Timer/Counter1 Output Compare Register contains the data to be continuously compared with Timer/Counter1. Actions on compare matches are specified in the Timer/Counter1 Control and Status registers.

Since the Output Compare Register (OCR1A) is a 16-bit register, a temporary register TEMP is used when OCR1A is written to ensure that both bytes are updated simultaneously. When the CPU writes the high byte, OCR1AH, the data is temporarily stored in the TEMP register. When the CPU writes the low byte, OCR1AL, the TEMP register is simultaneously written to OCR1AH. Consequently, the high byte OCR1AH must be written first for a full 16-bit register write operation.

The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program or interrupts if interrupts are re-enabled.


ICR1L and ICR1H
ICR1L and ICR1H -  Timer/Counter1 Input Capture Register

(ICR1L: I/O address: $24, SRAM address: $44 - ICR1H: I/O address: $25, SRAM address: $45)

ICR1L		ICR1H
Bit	R/W	Name	Init		Bit	R/W	Name	Init
7	R	Bit 7	0		7	R	Bit 14 (MSB)	0
6	R	Bit 6	0		6	R	Bit 14	0
5	R	Bit 5	0		5	R	Bit 13	0
4	R	Bit 4	0		4	R	Bit 12	0
3	R	Bit 3	0		3	R	Bit 11	0
2	R	Bit 2	0		2	R	Bit 10	0
1	R	Bit 1	0		1	R	Bit 9	0
0	R	Bit 0 (LSB)	0		0	R	Bit 8	0

The input capture register is a 16-bit read-only register.

When the rising or falling edge (according to the input capture edge setting [ICES1]) of the signal at the input capture pin (ICP) is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register (ICR1). At the same time, the input capture flag (ICF1) is set (one).

Since the Input Capture Register (ICR1) is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low byte ICR1L, the data is sent to the CPU and the data of the high byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low byte ICR1L must be accessed first for a full 16-bit register read operation.

The TEMP register is also used when accessing TCNT1 and OCR1A. If the main program and interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program or interrupts if interrupts are re-enabled.


WDTCR
WDTCR - Watchdog Timer Control Register (I/O address: $21, SRAM address: $41)

Bit	R/W	Name	Init	Comment
7	R	-	0	Reserved. Always read as zero.
6	R	-	0	Reserved. Always read as zero.
5	R	-	0	Reserved. Always read as zero.
4	R/W	WDTOE	0	Watchdog Turn-off Enable This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will not be disabled. Once set, hardware will clear this bit to zero after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure.
3	R/W	WDE	0	Watchdog Enable When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero), the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logical 1” to WDTOE and WDE. A logical 1” must be written to WDE even though it is set to 1 before the disable operation starts. 2. Within the next four clock cycles, write a logical 0” to WDE. This disables the Watchdog.
2 1 0	R/W R/W R/W	WDP2 WDP1 WDP0	0 0 0	Bits 2..0  WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0 The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. Here are the different prescaling values and their corresponding time-out periods: WDP2 WDP1 WDP0 WDT Typical Time-out Typical Time-out Cycles at VCC = 3.0V at VCC = 5.0V 0 0 0 16K cycles 47 ms 15 ms 0 0 1 32K cycles 94 ms 30 ms 0 1 0 64K cycles 0.19 s 60 ms 0 1 1 128K cycles 0.38 s 0.12 s 1 0 0 256K cycles 0.75 s 0,24 s 1 0 1 512K cycles 1.5 s 0.49 s 1 1 0 1,024K cycles 3.0 s 0.97 s 1 1 1 2,048K cycles 6.0 s 1.9 s
Note:	The frequency of the Watchdog Oscillator is voltage-dependent, as shown in the Electrical Characteristics section.
The WDR (Watchdog Reset) instruction should always be executed before the Watchdog Timer is enabled. This ensures that the reset period will be in accordance with the Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the Watchdog Timer may not start counting from zero.
To avoid unintentional MCU reset, the Watchdog Timer should be disabled or reset before changing the Watchdog Timer Prescale Select.


EEAR
EEAR - EEPROM Address Register (I/O address: $1E, SRAM address: $3E)

Bit	R/W	Name	Init	Comment
7	R	-	0	Reserved. Always read as zero.
6 5 4 3 2 1 0	R/W R/W R/W R/W R/W R/W R/W	EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0	0 0 0 0 0 0 0	Bit 6..0  EEAR6..0: EEPROM Address The EEPROM Address Register (EEAR6..0) specifies the EEPROM address in the 128 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127.


EEDR
EEDR - EEPROM Data Register (I/O address: $1D, SRAM address: $3D)

Bit	R/W	Name	Init	Comment
7 6 5 4 3 2 1 0	R/W R/W R/W R/W R/W R/W R/W R/W	MSB LSB	0 0 0 0 0 0 0 0	Bit 7..0  EEDR7..0: EEPROM Data For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.


EECR
EECR - EEPROM Control Register (I/O address: $1C, SRAM address: $3C)

Bit	R/W	Name	Init	Comment
7	R	-	0	Reserved. Always read as zero.
6	R	-	0	Reserved. Always read as zero.
5	R	-	0	Reserved. Always read as zero.
4	R	-	0	Reserved. Always read as zero.
3	R	-	0	Reserved. Always read as zero.
2	R/W	EEMWE	0	EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set (one), setting EEWE will write data to the EEPROM at the selected address. If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been set (one) by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for a EEPROM write procedure.
1	R/W	EEWE	0	EEPROM Write Enable The EEPROM Write Enable Signal (EEWE) is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. The EEMWE bit must be set when the logical 1” is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 2 and 3 is unessential): 1. Wait until EEWE becomes zero. 2. Write new EEPROM address to EEAR (optional). 3. Write new EEPROM data to EEDR (optional). 4. Write a logical 1” to the EEMWE bit in EECR (to be able to write a logical 1” to the EEMWE bit, the EEWE bit must be written to zero in the same cycle). 5. Within four clock cycles after setting EEMWE, write a logical 1” to EEWE. When the write access time (typically 2.5 ms at VCC = 5V or 4 ms at VCC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. Caution: An interrupt between step 4 and step 5 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the global interrupt flag cleared during the last four steps to avoid these problems.
0	R/W	EERE	0	EEPROM Read Enable The EEPROM Read Enable Signal (EERE) is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress when new data or address is written to the EEPROM I/O registers, the write operation will be interrupted and the result is undefined.


UDR
UDR - UART Data Register (I/O address: $0C, SRAM address: $2C)

Bit	R/W	Name	Init	Comment
7	R/W	MSB	0
6	R/W		0
5	R/W		0
4	R/W		0
3	R/W		0
2	R/W		0
1	R/W		0
0	R/W	LSB	0

The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. When reading from UDR, the UART Receive Data register is read.


USR
USR - UART Status Register (I/O address: $0B, SRAM address: $2B)

The USR register is a read-only register providing information on the UART status.

Bit	R/W	Name	Init	Comment
7	R	RXC	0	UART Receive Complete This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR. The bit is set regardless of any detected framing errors. When the RXCIE bit in UCR is set, the UART Receive Complete interrupt will be executed when RXC is set (one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the interrupt routine terminates.
6	R	TXC	0	UART Transmit Complete This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and no new data has been written to UDR. This flag is especially useful in half-duplex communications interfaces, where a transmitting  application must enter receive mode and free the communications bus immediately after completing the transmission. When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared (zero) by writing a logical 1” to the bit.
5	R	UDRE	0	UART Data Register Empty This bit is set (one) when a character written to UDR is transferred to the Transmit shift register. Setting of this bit indicates that the transmitter is ready to receive a new character for transmission. When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt is executed as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates. UDRE is set (one) during reset to indicate that the transmitter is ready.
4	R	FE	0	Framing Error This bit is set if a Framing Error condition is detected (i.e., when the stop bit of an incomingcharacter is zero). The FE bit is cleared when the stop bit of received data is one.
3	R	OR	0	Overrun This bit is set if an Overrun condition is detected (i.e., when a character already present in the UDR register is not read before the next character has been shifted into the Receiver Shift register). The OR bit is buffered, which means that it will be set once the valid data still in UDRE is read. The OR bit is cleared (zero) when data is received and transferred to UDR.
2	R	-	0	Reserved. Always read as zero.
1	R	-	0	Reserved. Always read as zero.
0	R	-	0	Reserved. Always read as zero.


UCR
UCR - UART Control Register (I/O address: $0A, SRAM address: $2A)

Bit	R/W	Name	Init	Comment
7	R/W	RXCIE	0	RX Complete Interrupt Enable When this bit is set (one), a setting of the RXC bit in USR will cause the Receive CompleteInterrupt routine to be executed provided that global interrupts are enabled.
6	R/W	TXCIE	0	TX Complete Interrupt Enable When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete Interrupt routine to be executed provided that global interrupts are enabled.
5	R/W	UDRIE	0	UART Data Register Empty Interrupt Enable When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register Empty Interrupt routine to be executed provided that global interrupts are enabled.
4	R/W	RXEN	0	Receiver Enable This bit enables the UART receiver when set (one). When the receiver is disabled, the RXC, OR and FE status flags cannot become set. If these flags are set, turning off RXEN does not cause them to be cleared.
3	R/W	TXEN	0	Transmitter Enable This bit enables the UART transmitter when set (one). When disabling the transmitter while transmitting a character, the transmitter is not disabled before the character in the shift register plus any following character in UDR has been completely transmitted.
2	R/W	CHR9	0	9 Bit Characters When this bit is set (one), transmitted and received characters are nine bits long plus start and stop bits. The ninth bit is read and written by using the RXB8 and TXB8 bits in UCR, respectively. The ninth data bit can be used as an extra stop bit or a parity bit.
1	R	RXB8	1	Receive Data Bit 8 When CHR9 is set (one), RXB8 is the ninth data bit of the received character.
0	R/W	TXB8	0	Transmit Data Bit 8 When CHR9 is set (one), TXB8 is the ninth data bit in the character to be transmitted.


UBRR
UBRR - UART Baud Rate Register (I/O address: $09, SRAM address: $29)

Bit	R/W	Name	Init	Comment
7	R/W	MSB	0
6	R/W		0
5	R/W		0
4	R/W		0
3	R/W		0
2	R/W		0
1	R/W		0
0	R/W	LSB	0

The UBRR register is an 8-bit read/write register that specifies the UART Baud Rate.

The baud rate generator divides the baud rate from the MCU clock according to the following equation:

	• BAUD: Baud Rate • fClock: Crystal Clock frequency • UBRR: Contents of the UART Baud Rate register (UBRR) (0 - 255)

Note: Baud rates that have more than 1% error is not recommended. High error ratings give less noise resistance.


ACSR
ACSR - Analog Comparator Control and Status Register (I/O address: $08, SRAM address: $28)

Bit	R/W	Name	Init	Comment
7	R/W	ACD	0	Analog Comparator Disable When this bit is set (one), the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in active and idle modes. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
6	R	-	0	Reserved. Always read as zero.
5	R	ACO	N/A	Analog Comparator Output ACO is directly connected to the comparator output.
4	R/W	ACI	0	Analog Comparator Interrupt Flag This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logical 1” to the flag. Observe, however, that if another bit in this register is modified using the SBI or CBI instruction, ACI will be cleared if it has become set before the operation.
3	R/W	ACIE	0	Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the Analog Comparator interrupt is activated. When cleared (zero), the interrupt is disabled.
2	R/W	ACIC	0	Analog Comparator Input Capture Enable When set (one), this bit enables the Input Capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is, in this case, directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge-select features of the Timer/Counter1 Input Capture interrupt. When cleared (zero), no connection between the Analog Comparator and the Input Capture function is given. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set (one).
1 0	R/W R/W	ACIS1 ACIS0	0 0	Bits 1,0  ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events trigger the Analog Comparator interrupt. The different settings are shown in the following table: ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge 1 1 Comparator Interrupt on Rising Output Edge Note: When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR register. Otherwise an interrupt can occur when the bits are changed.


Init: The initial value after Reset


R/W: Read/Write access

R:	Read only

W:	Write only

R/W:	Read and write


MSB: Most significant bit


LSB: Least significant bit


Complete Instruction Set Summary
Complete Instruction Set Summary	Nomenclature

Arithmetic and Logic Instructions

Mnemonic	Operands	Description	Operation	Flags	Clocks
ADD	Rd, Rr	Add without Carry	Rd ← Rd + Rr	Z,C,N,V,S,H	1
ADC	Rd, Rr	Add with Carry	Rd ← Rd + Rr + C	Z,C,N,V,S,H	1
ADIW	Rd, K	Add Immediate to Word	Rd+1:Rd ← Rd+1:Rd + K	Z,C,N,V,S	2
SUB	Rd, Rr	Subtract without Carry	Rd ← Rd - Rr	Z,C,N,V,S,H	1
SUBI	Rd, K	Subtract Immediate	Rd ← Rd - K	Z,C,N,V,S,H	1
SBC	Rd, Rr	Subtract with Carry	Rd ← Rd - Rr - C	Z,C,N,V,S,H	1
SBCI	Rd, K	Subtract Immediate with Carry	Rd ← Rd - K - C	Z,C,N,V,S,H	1
SBIW	Rd, K	Subtract Immediate from Word	Rd+1:Rd ← Rd+1:Rd - K	Z,C,N,V,S	2
AND	Rd, Rr	Logical AND	Rd ← Rd • Rr	Z,N,V,S	1
ANDI	Rd, K	Logical AND with Immediate	Rd ← Rd • K	Z,N,V,S	1
OR	Rd, Rr	Logical OR	Rd ← Rd ∨ Rr	Z,N,V,S	1
ORI	Rd, K	Logical OR with Immediate	Rd ← Rd ∨ K	Z,N,V,S	1
EOR	Rd, Rr	Exclusive OR	Rd ← Rd ⊕ Rr	Z,N,V,S	1
COM	Rd	Ones Complement	Rd ← $FF - Rd	Z,C,N,V,S	1
NEG	Rd	Twos Complement	Rd ← $00 - Rd	Z,C,N,V,S,H	1
SBR	Rd,K	Set Bit(s) in Register	Rd ← Rd ∨ K	Z,N,V,S	1
CBR	Rd,K	Clear Bit(s) in Register	Rd ← Rd • ($FFh - K)	Z,N,V,S	1
INC	Rd	Increment	Rd ← Rd + 1	Z,N,V,S	1
DEC	Rd	Decrement	Rd ← Rd - 1	Z,N,V,S	1
TST	Rd	Test for Zero or Minus	Rd ← Rd • Rd	Z,N,V,S	1
CLR	Rd	Clear Register	Rd  ← Rd ⊕ Rd	Z,N,V,S	1
SER	Rd	Set Register	Rd ← $FF	None	1
MUL	Rd,Rr	Multiply Unsigned	R1:R0 ← Rd × Rr (UU)	Z,C	2
MULS	Rd,Rr	Multiply Signed	R1:R0 ← Rd × Rr (SS)	Z,C	2
MULSU	Rd,Rr	Multiply Signed with Unsigned	R1:R0 ← Rd × Rr (SU)	Z,C	2
FMUL	Rd,Rr	Fractional Multiply Unsigned	R1:R0 ← (Rd × Rr)<<1 (UU)	Z,C	2
FMULS	Rd,Rr	Fractional Multiply Signed	R1:R0 ← (Rd × Rr)<<1 (SS)	Z,C	2
FMULSU	Rd,Rr	Fractional Multiply Signed with Unsigned	R1:R0 ← (Rd × Rr)<<1 (SU)	Z,C	2

Branch Instructions

Mnemonic	Operands	Description	Operation	Flags	Clocks
RJMP	k	Relative Jump	PC ← PC + k + 1	None	2
IJMP		Indirect Jump to (Z)	PC(15:0) ← Z, PC(21:16) ← 0	None	2
EIJMP		Extended Indirect Jump to (Z)	PC(15:0) ← Z, PC(21:16) ← EIND	None	2
JMP	k	Jump	PC ← k	None	3
RCALL	k	Relative Call Subroutine	PC ← PC + k + 1	None	3 / 4
ICALL		Indirect Call to (Z)	PC(15:0) ← Z, PC(21:16) ← 0	None	3 / 4
EICALL		Extended Indirect Call to (Z)	PC(15:0) ← Z, PC(21:16) ← EIND	None	4
CALL	k	Call Subroutine	PC ← k	None	4 / 5
RET		Subroutine Return	PC ← STACK	None	4 / 5
RETI		Interrupt Return	PC ← STACK	I	4 / 5
CPSE	Rd,Rr	Compare, Skip if Equal	if (Rd = Rr) PC ← PC + 2 or 3	None	1 / 2 / 3
CP	Rd,Rr	Compare	Rd - Rr	Z,C,N,V,S,H	1
CPC	Rd,Rr	Compare with Carry	Rd - Rr - C	Z,C,N,V,S,H	1
CPI	Rd,K	Compare with Immediate	Rd - K	Z,C,N,V,S,H	1
SBRC	Rr, b	Skip if Bit in Register Cleared	if (Rr(b)=0) PC ← PC + 2 or 3	None	1 / 2 / 3
SBRS	Rr, b	Skip if Bit in Register Set	if (Rr(b)=1) PC ← PC + 2 or 3	None	1 / 2 / 3
SBIC	A, b	Skip if Bit in I/O Register Cleared	if(I/O(A,b)=0) PC ← PC + 2 or 3	None	1 / 2 / 3
SBIS	A, b	Skip if Bit in I/O Register Set	If(I/O(A,b)=1) PC ← PC + 2 or 3	None	1 / 2 / 3
BRBS	s, k	Branch if Status Flag Set	if (SREG(s) = 1) then PC ←PC+k + 1	None	1 / 2
BRBC	s, k	Branch if Status Flag Cleared	if (SREG(s) = 0) then PC ←PC+k + 1	None	1 / 2
BREQ	k	Branch if Equal	if (Z = 1) then PC ← PC + k + 1	None	1 / 2
BRNE	k	Branch if Not Equal	if (Z = 0) then PC ← PC + k + 1	None	1 / 2
BRCS	k	Branch if Carry Set	if (C = 1) then PC ← PC + k + 1	None	1 / 2
BRCC	k	Branch if Carry Cleared	if (C = 0) then PC ← PC + k + 1	None	1 / 2
BRSH	k	Branch if Same or Higher	if (C = 0) then PC ← PC + k + 1	None	1 / 2
BRLO	k	Branch if Lower	if (C = 1) then PC ← PC + k + 1	None	1 / 2
BRMI	k	Branch if Minus	if (N = 1) then PC ← PC + k + 1	None	1 / 2
BRPL	k	Branch if Plus	if (N = 0) then PC ← PC + k + 1	None	1 / 2
BRGE	k	Branch if Greater or Equal, Signed	if (N ⊕ V= 0) then PC ← PC + k + 1	None	1 / 2
BRLT	k	Branch if Less Than, Signed	if (N ⊕ V= 1) then PC ← PC + k + 1	None	1 / 2
BRHS	k	Branch if Half Carry Flag Set	if (H = 1) then PC ← PC + k + 1	None	1 / 2
BRHC	k	Branch if Half Carry Flag Cleared	if (H = 0) then PC ← PC + k + 1	None	1 / 2
BRTS	k	Branch if T Flag Set	if (T = 1) then PC ← PC + k + 1	None	1 / 2
BRTC	k	Branch if T Flag Cleared	if (T = 0) then PC ← PC + k + 1	None	1 / 2
BRVS	k	Branch if Overflow Flag is Set	if (V = 1) then PC ← PC + k + 1	None	1 / 2
BRVC	k	Branch if Overflow Flag is Cleared	if (V = 0) then PC ← PC + k + 1	None	1 / 2
BRIE	k	Branch if Interrupt Enabled	if ( I = 1) then PC ← PC + k + 1	None	1 / 2
BRID	k	Branch if Interrupt Disabled	if ( I = 0) then PC ← PC + k + 1	None	1 / 2

Data Transfer Instructions

Mnemonic	Operands	Description	Operation	Flags	Clocks
MOV	Rd, Rr	Copy Register	Rd ← Rr	None	1
MOVW	Rd, Rr	Copy Register Pair	Rd+1:Rd ← Rr+1:Rr	None	1
LDI	Rd, K	Load Immediate	Rd  ← K	None	1
LDS	Rd, k	Load Direct from data space	Rd ← (k)	None	2
LD	Rd, X	Load Indirect	Rd ← (X)	None	2
LD	Rd, X+	Load Indirect and Post-Increment	Rd ← (X), X ← X + 1	None	2
LD	Rd, -X	Load Indirect and Pre-Decrement	X ← X - 1, Rd ← (X)	None	2
LD	Rd, Y	Load Indirect	Rd ← (Y)	None	2
LD	Rd, Y+	Load Indirect and Post-Increment	Rd ← (Y), Y ← Y + 1	None	2
LD	Rd, -Y	Load Indirect and Pre-Decrement	Y ← Y - 1, Rd ← (Y)	None	2
LDD	Rd,Y+q	Load Indirect with Displacement	Rd ← (Y + q)	None	2
LD	Rd, Z	Load Indirect	Rd ← (Z)	None	2
LD	Rd, Z+	Load Indirect and Post-Increment	Rd ← (Z), Z ← Z+1	None	2
LD	Rd, -Z	Load Indirect and Pre-Decrement	Z ← Z - 1, Rd ← (Z)	None	2
LDD	Rd, Z+q	Load Indirect with Displacement	Rd ← (Z + q)	None	2
STS	k, Rr	Store Direct to data space	Rd ← (k)	None	2
ST	X, Rr	Store Indirect	(X) ← Rr	None	2
ST	X+, Rr	Store Indirect and Post-Increment	(X) ← Rr, X ← X + 1	None	2
ST	-X, Rr	Store Indirect and Pre-Decrement	X ← X - 1, (X) ← Rr	None	2
ST	Y, Rr	Store Indirect	(Y) ← Rr	None	2
ST	Y+, Rr	Store Indirect and Post-Increment	(Y) ← Rr, Y ← Y + 1	None	2
ST	-Y, Rr	Store Indirect and Pre-Decrement	Y ← Y - 1, (Y) ← Rr	None	2
STD	Y+q,Rr	Store Indirect with Displacement	(Y + q) ← Rr	None	2
ST	Z, Rr	Store Indirect	(Z) ← Rr	None	2
ST	Z+, Rr	Store Indirect and Post-Increment	(Z) ← Rr, Z ← Z + 1	None	2
ST	-Z, Rr	Store Indirect and Pre-Decrement	Z ← Z - 1, (Z) ← Rr	None	2
STD	Z+q,Rr	Store Indirect with Displacement	(Z + q) ← Rr	None	2
LPM		Load Program Memory	R0 ← (Z)	None	3
LPM	Rd, Z	Load Program Memory	Rd ← (Z)	None	3
LPM	Rd, Z+	Load Program Memory and Post-Increment	Rd ← (Z), Z ← Z + 1	None	3
ELPM		Extended Load Program Memory	R0 ← (RAMPZ:Z)	None	3
ELPM	Rd, Z	Extended Load Program Memory	Rd ← (RAMPZ:Z)	None	3
ELPM	Rd, Z+	Extended Load Program Memory and Post-Increment	Rd ← (RAMPZ:Z), Z ← Z + 1	None	3
SPM		Store Program Memory	(Z) ← R1:R0	None	-
ESPM		Extended Store Program Memory	(RAMPZ:Z) ← R1:R0	None	-
IN	Rd, A	In From I/O Location	Rd ← I/O(A)	None	1
OUT	A, Rr	Out To I/O Location	I/O(A) ← Rr	None	1
PUSH	Rr	Push Register on Stack	STACK ← Rr	None	2
POP	Rd	Pop Register from Stack	Rd ← STACK	None	2

Bit and Bit-test Instructions

Mnemonic	Operands	Description	Operation	Flags	Clocks
LSL	Rd	Logical Shift Left	Rd(n+1)←Rd(n),Rd(0)←0,C←Rd(7)	Z,C,N,V,H	1
LSR	Rd	Logical Shift Right	Rd(n)←Rd(n+1),Rd(7)←0,C←Rd(0)	Z,C,N,V	1
ROL	Rd	Rotate Left Through Carry	Rd(0)←C,Rd(n+1)←Rd(n),C←Rd(7)	Z,C,N,V,H	1
ROR	Rd	Rotate Right Through Carry	Rd(7)←C,Rd(n)←Rd(n+1),C←Rd(0)	Z,C,N,V	1
ASR	Rd	Arithmetic Shift Right	Rd(n) ← Rd(n+1), n=0..6	Z,C,N,V	1
SWAP	Rd	Swap Nibbles	Rd(3..0) ↔ Rd(7..4)	None	1
BSET	s	Flag Set	SREG(s) ← 1	SREG(s)	1
BCLR	s	Flag Clear	SREG(s) ← 0	SREG(s)	1
SBI	A, b	Set Bit in I/O Register	I/O(A, b) ← 1	None	2
CBI	A, b	Clear Bit in I/O Register	I/O(A, b) ← 0	None	2
BST	Rr, b	Bit Store from Register to T	T ← Rr(b)	T	1
BLD	Rd, b	Bit load from T to Register	Rd(b) ← T	None	1
SEC		Set Carry	C ← 1	C	1
CLC		Clear Carry	C ← 0	C	1
SEN		Set Negative Flag	N ← 1	N	1
CLN		Clear Negative Flag	N ← 0	N	1
SEZ		Set Zero Flag	Z ← 1	Z	1
CLZ		Clear Zero Flag	Z ← 0	Z	1
SEI		Global Interrupt Enable	I ← 1	I	1
CLI		Global Interrupt Disable	I ← 0	I	1
SES		Set Signed Test Flag	S ← 1	S	1
CLS		Clear Signed Test Flag	S ← 0	S	1
SEV		Set Twos Complement Overflow	V ← 1	V	1
CLV		Clear Twos Complement Overflow	V ← 0	V	1
SET		Set T in SREG	T ← 1	T	1
CLT		Clear T in SREG	T ← 0	T	1
SEH		Set Half Carry Flag in SREG	H ← 1	H	1
CLH		Clear Half Carry Flag in SREG	H ← 0	H	1
NOP		No Operation		None	1
SLEEP		Sleep	(see specific descr. for Sleep)	None	1
WDR		Watchdog Reset	(see specific descr. for WDR)	None	1

Notes:

1.	Not all instructions are available in all devices. Instructions not available for AT90S2313 are gray.

2.	Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface. For LD, ST, LDS, STS, PUSH, POP, add one cycle plus one cycle for each wait state. For CALL, ICALL, EICALL, RCALL, RET, RETI in devices with 16 bit PC, add three cycles plus two cycles for each wait state. For CALL, ICALL, EICALL, RCALL, RET, RETI in devices with 22 bit PC, add five cycles plus three cycles for each wait state.

Conditional Branch Summary

Test	Boolean	Mnemonic	Complementary	Boolean	Mnemonic	Comment
Rd > Rr	Z•(N ⊕ V) = 0	BRLT*	Rd ≤ Rr	Z+(N ⊕ V) = 1	BRGE*	Signed
Rd ≥  Rr	(N ⊕ V) = 0	BRGE	Rd < Rr	(N ⊕ V) = 1	BRLT	Signed
Rd = Rr	Z = 1	BREQ	Rd ≠ Rr	Z = 0	BRNE	Signed
Rd ≤  Rr	Z+(N ⊕ V) = 1	BRGE*	Rd > Rr	Z•(N ⊕ V) = 0	BRLT*	Signed
Rd < Rr	(N ⊕ V) = 1	BRLT	Rd ≥ Rr	(N ⊕ V) = 0	BRGE	Signed
Rd > Rr	C + Z = 0	BRLO*	Rd ≤ Rr	C + Z = 1	BRSH*	Unsigned
Rd ≥  Rr	C = 0	BRSH/BRCC	Rd < Rr	C = 1	BRLO/BRCS	Unsigned
Rd = Rr	Z = 1	BREQ	Rd ≠ Rr	Z = 0	BRNE	Unsigned
Rd ≤  Rr	C + Z = 1	BRSH*	Rd > Rr	C + Z = 0	BRLO*	Unsigned
Rd < Rr	C = 1	BRLO/BRCS	Rd ≥ Rr	C = 0	BRSH/BRCC	Unsigned
Carry	C = 1	BRCS	No carry	C = 0	BRCC	Simple
Negative	N = 1	BRMI	Positive	N = 0	BRPL	Simple
Overflow	V = 1	BRVS	No overflow	V = 0	BRVC	Simple
Zero	Z = 1	BREQ	Not zero	Z = 0	BRNE	Simple

*Note: Interchange Rd and Rr in the operation before the test. i.e. CP Rd,Rr → CP Rr,Rd


Nomenclature

RAMPX, RAMPY, RAMPZ	Registers concatenated with the X, Y and Z registers enabling indirect addressing of the whole data space on MCUs with more than 64K bytes data space, and constant data fetch on MCUs with more than 64K bytes program space.

RAMPD	Register concatenated with the Z register enabling direct addressing of the whole data space on MCUs with more than 64K bytes data space.

EIND	Register concatenated with the instruction word enabling indirect jump and call to the whole program space on MCUs with more than 64K bytes program space.

STACK	Stack for return address and pushed registers

SP	Stack Pointer to STACK

SREG	Status register

C	Carry flag

Z	Zero flag

N	Negative flag

V	Twos complement overflow indicator

S	N ⊕ V, For signed tests

H	Half Carry flag in the status register

T	Transfer bit used by BLD and BST instructions

I	Global interrupt enable/disable flag

Flag symbols

⇔	Flag affected by instruction

0	Flag cleared by instruction

1	Flag set by instruction

-	Flag not affected by instruction

Registers and Operands

Rd	Destination (and source) register in the register file

Rr	Source register in the register file

R	Result after instruction is executed

K	Constant data

k	Constant address

b	Bit in the register file or I/O register (3 bit)

s	Bit in the status register (3 bit)

X,Y,Z	Indirect address register
(X=R27:R26, Y=R29:R28 and Z=R31:R30)

A	I/O location address

q	Displacement for direct addressing (6 bit)

Numerical symbols

⊕	EOR (XOR, Exclusive OR)

←	Implication (left follows from right)

•	AND

≤	smaller equal

∈	Element of...

≠	Not equal

≥	greater equal

→	Implication (right follows from left)

×	Multiply

↔	Equivalence (right and left is equivalent)

+	Add

-	Subtract

:	Separates HiByte:LoByte of a Word

∨	OR

<<	Shift left

>>	Shift right